Projects
RISC-V SoCs, ASIC physical design and FPGA / embedded projects. Public source, implementation details and verification results.
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32-bit RISC-V SoC · TEKNOFEST 2026
BLogic MCU
FeaturedBuilt with the BLogic Mikroelektronik team: a CV32E40P-based microcontroller with AXI4 interconnect, peripherals and a TinyConv keyword-spotting accelerator. Verified in simulation, running on Genesys 2, with a completed SKY130 RTL-to-GDS flow.
- Architecture
- RV32IMC
- FPGA
- 50 MHz
- ASIC signoff
- 27 MHz
SKY130 · GDS layout -
8-bit Counter ASIC
Repo
A VHDL synchronous counter taken from simulation to SKY130 GDS with LibreLane. The core passes DRC, LVS and timing checks; the separate I/O pad ring is an educational experiment.
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Verilog
RepoVerilog RTL work: finite state machine examples, general digital-design exercises, and a UART-driven LED project targeting the Digilent Basys 3 board.
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VHDL
RepoVHDL fundamentals built up from gates to datapaths: logic gates, a full adder and 4-bit ripple-carry adder, multiplexers, decoder/encoder, D flip-flop, clock division, FSM examples and button-controlled LED projects.
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NFC System Project
RepoEmbedded C++ coursework project built with Muhammed Bucak — an NFC-based identification and access system.
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berkkuzu.com
This siteNo framework and no build step — plain HTML, CSS and JavaScript on GitHub Pages. The learning log renders from a JSON file, and a scheduled GitHub Action regenerates the contribution graph every day.