Work

Projects

Hardware first — RTL and embedded work I have written myself. Every card with a repo badge links to public source.

Verilog
Repo

Verilog RTL work: finite state machine examples, general digital-design exercises, and a UART-driven LED project targeting the Digilent Basys 3 board.
- Verilog
- FSM
- UART
- Basys 3
- Vivado
VHDL
Repo

VHDL fundamentals built up from gates to datapaths: logic gates, a full adder and 4-bit ripple-carry adder, multiplexers, decoder/encoder, D flip-flop, clock division, FSM examples and button-controlled LED projects.
- VHDL
- Combinational logic
- Sequential logic
- FSM
- FPGA
NFC System Project
Repo

Embedded C++ coursework project built with Muhammed Bucak — an NFC-based identification and access system.
- C++
- Embedded
- NFC / RFID
MCU architecture
2026 finalist

Our own MCU for the TEKNOFEST Chip Design competition, designed with the Ostim BLogic Microelectronics team I founded and captain. Passed the ÖTR preliminary design report stage. My role is RTL design and FPGA prototyping on a Genesys 2 (Kintex-7). Source is not public yet.
- RTL
- MCU
- Chip design
- Genesys 2
- TEKNOFEST
berkkuzu.com
This site

No framework and no build step — plain HTML, CSS and JavaScript on GitHub Pages. The learning log renders from a JSON file, and a scheduled GitHub Action regenerates the contribution graph every day.
- HTML
- CSS
- JavaScript
- GitHub Actions
- GitHub Pages