Projects / VHDL problem sets
VHDL problem sets
A hands-on VHDL book. Each chapter explains part of the language with examples that run right on the page, then gives you circuits to write: you write the architecture, press Check, and your design is simulated against a reference.
How the checker works
The checker is a VHDL-2008 simulator written in JavaScript. It parses, type-checks and
simulates your code right here in your browser; nothing is uploaded. Every test vector
is applied in turn and every output is compared with the reference, so wrong values,
latches, missing sensitivity entries and 'U' outputs all show up.
It covers the synthesizable VHDL these problems use: std_logic and its vectors,
numeric_std, processes, generics, generate, functions, enumerated
types and VHDL-2008 additions such as process(all), case? and the
reduction operators. It also runs testbenches in simulated time: after delays,
wait statements, assertions and std.env.finish. Records, procedures, files and
real numbers are not supported. Every reference solution and every example of the chapters
has also been run in GHDL with the same inputs.
The circuits are the classics of digital design textbooks, such as those by Mano, Wakerly, Brown and Vranesic, Harris and Harris, Pedroni and Chu: majority voters, comparators, adder-subtractors, shift registers, LFSRs, Hamming codes, sequence detectors and double dabble. The problems and their texts are written for this page, with extra ones on what VHDL does differently. Your code and progress stay in this browser.