Digital Design Engineer
Berk Muammer Kuzu
Digital design · FPGA / SoC · Embedded Systems
Digital Design Engineer at ANADOLOGIC
Electric & Electronic Engineer
Latest entries
Short write-ups of things I worked out recently — RTL, timing, toolchains, and the occasional mistake worth remembering.
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No entries yet…
Projects
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32-bit RISC-V SoC · TEKNOFEST 2026
BLogic MCU
FeaturedBuilt with the BLogic Mikroelektronik team: a CV32E40P-based microcontroller with AXI4 interconnect, peripherals and a TinyConv keyword-spotting accelerator. Verified in simulation, running on Genesys 2, with a completed SKY130 RTL-to-GDS flow.
- Architecture
- RV32IMC
- FPGA
- 50 MHz
- ASIC signoff
- 27 MHz
SKY130 · GDS layout -
8-bit Counter ASIC
Repo
A VHDL synchronous counter taken from simulation to SKY130 GDS with LibreLane. The core passes DRC, LVS and timing checks; the separate I/O pad ring is an educational experiment.
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Verilog
RepoRTL work in Verilog: finite state machines, digital-design exercises and a UART-driven LED project on the Digilent Basys 3.
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VHDL
RepoFundamentals built up from gates to datapaths — adders, multiplexers, flip-flops, clock division and FSM examples.
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NFC System
RepoAn NFC-based identification and access system, written in embedded C++ with Muhammed Bucak.
GitHub activity
Contributions over the last 12 months, updated daily.
